DVCon 2012 "Day 0": UVM tutorial

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    It's clear UVM is being widely adopted since this tutorial was packed, and the questions were detailed in a way that suggested they were inspired by real world usage. Here, R&D Solutions Architect Kathleen Meade reviews flexibility UVM allows to leverage / reuse of code.

    (Related note: as Jason Sprauge cautioned in this video interview on his award winning paper, "Yikes - why is my SystemVerilog testbench so Slooooow": youtu.be/CeGJGOUgCqg this freedom also comes with responsibility.

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